View E5551A-DIT_737274.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

e5551 rev. a2, 19-apr-00 1 (21) standard r/w identification ic with anticollision description the e5551 is a contactless r/w- id entification ic (idic ? )* for general-purpose applications in the 125 khz range. a single coil, connected to the chip, serves as the ic?s power supply and bidirectional communication interface. coil and chip together form a transponder. the on-chip 264-bit eeprom (8 blocks 33 bits each) can be read and written blockwise from a base station. the blocks can be protected against overwriting. one block is reserved for setting the operation modes of the ic. another block can contain a password to prevent unauthorized writing. reading occurs by damping the coil by an internal load. there are different bitrates and encoding schemes possible. writing occurs by interrupting the rf field in a special way. features low-power, low-voltage operation contactless power supply contactless read/write data transmission r adio f requency (rf): 100 khz to 150 khz 264 bit eeprom memory in 8 blocks of 33 bits 224 bits in 7 blocks of 32 bits are free for user data block write protection extensive protection against contactless malpro- gramming of the eeprom anticollision using answer-on-request (aor) typical < 50 ms to write and verify a block other options set by eeprom: bitrate [bit/s]: rf/8, rf/16, rf/32, rf/40 rf/50, rf/64, rf/100, rf/128 modulation: bin, fsk, psk, manchester, biphase other: terminator mode, password mode controller coil interface memory transponder base station data power controller coil interface memory transponder base station data power e5551 figure 1. rfid system using e5551 tag ordering information extended type number package remarks e5551a-dow E5551A-DIT e5551a-fp008 dow dice in tray so8 configuration after production test is an erased memory (?0?) * idic ? stands for identification integrated circuit and is a trademark of temic semiconductors
e5551 rev. a2, 19-apr-00 2 (21) pads name pad window function coil1 136 136 m 2 1st coil pad coil2 136 136 m 2 2nd coil pad v dd 78 78 m 2 positive supply voltage v ss 78 78 m 2 negative supply voltage (gnd) test1 78 78 m 2 test pad test2 78 78 m 2 test pad test3 78 78 m 2 test pad coil 1 coil 2 1 2 3 4 8 7 6 5 e5551 note: pins 2 to 7 have to be open. they are not specified for applications figure 2. pinning so8 e5551 building blocks analog front end (afe) the afe includes all circuits which are directly connected to the coil. it generates the ic ? s power supply and handles the bidirectional data communication with the reader unit. it consists of the following blocks: rectifier to generate a dc supply voltage from the ac coil voltage clock extractor switchable load between coil1/ coil2 for data trans- mission from the ic to the reader unit (read) field gap detector for data transmission from the reader unit into the ic (write) controller the main controller has following functions: load mode register with configuration data from eeprom block 0 after power-on and also during reading control memory access (read, write) handle write data transmission and the write error modes the first two bits of the write data stream are the op- code. there are two valid op-codes (standard and stop) which are decoded by the controller. in password mode, the 32 bits received after the op- code are compared with the stored password in block 7. bitrate generator the bitrate generator can deliver the following bitrates: rf/8 - rf/16 - rf/32 - rf/40 - rf/50 - rf/64 - rf/100 - rf/128 write decoder decode the detected gaps during writing. check if write data stream is valid. test logic test circuitry allows rapid programming and verification of the ic during test. hv generator voltage pump which generates 18 v for programming of the eeprom. pad layout coil 1 coil 2 vv test pads dd ss e5551 figure 3. pad layout
e5551 rev. a2, 19-apr-00 3 (21) coil 1 coil 2 modulator analog front end por input register write decoder bitrate generator memory (264 bit eeprom) controller test logic mode register hv generator v test pads dd v ss figure 4. block diagram e5551 power-on reset (por) the power-on reset is a delay reset which is triggered when supply voltage is applied. mode register the mode register stores the mode data from eeprom block 0. it is continually refreshed at the start of every block. this increases the reliability of the device (if the originally loaded mode information is false, it will be corrected by subsequent refresh cycles). modulator the modulator consists of several data encoders in two stages, which may be freely combined to obtain the desired modulation. the basic types of modulation are: psk: phase shift: 1) every change; 2) every ? 1 ? ; 3) every rising edge (carrier: fc/2, fc/4 or fc/8) fsk: 1) f1 = rf/8 f2 = rf/5; 2) f1 = rf/8, f2 = rf/10 manchester: rising edge = h; falling edge = l biphase: every bit creates a change, a data ? h ? creates an additional mid-bit change note: the following modulation type combinations will not work: stage1 manchester or biphase, stage2 psk2, at any psk carrier frequency (because the first stage output frequency is higher than the second stage strobe frequency) stage1 manchester or biphase and stage2 psk with bitrate = rf/8 and psk carrier frequency = rf/8 (for the same reason as above) any stage1 option with any psk for bitrates rf/50 or rf/100 if the psk carrier frequency is not an integer multiple of the bitrate (e.g., br = rf/50, pskcf = rf/4, because 50/4 = 12.5). this is because the psk carrier frequency must maintain constant phase with respect to the bit clock.
e5551 rev. a2, 19-apr-00 4 (21) memory the memory of the e5551 is a 264 bit eeprom, which is arranged in 8 blocks of 33 bits each. all 33 bits of a block, including the lock bit, are programmed simulta- neously. the programming voltage is generated on-chip. block 0 contains the mode data, which are not normally transmitted (see figure 6). block 1 to 6 are freely programmable. block 7 may be used as a password. if password protection is not required, it may be used for user data. bit 0 of every block is the lock bit for that block. once locked, the block (including the lockbit itself) cannot be field-reprogrammed. data from the memory is transmitted serially, starting with block 1, bit 1, up to block ? maxblk ? , bit 32. ? maxblk ? is a mode parameter set by the user to a value between 0 and 7 (if maxblk=0, only block 0 will be trans- mitted). block 7 block 6 block 5 block 4 block 3 block 2 block 1 block 0 user data or password 32 bits user data user data user data user data user data user data configuration data 132 0 l l l l l l l l not transmitted figure 5. memory map direct manchester biphase psk1 psk2 psk3 direct fsk1, 1a fsk2, 2a from memory to load carrier frequency mux mux figure 6. modulator block diagram
e5551 rev. a2, 19-apr-00 5 (21) maxblk 32 reserved 0 11 25 27 15 [2] [1] [0] ms2 18 20 [2] [1] [0] ms1 16 17 [1] [0] 31 30 29 28 24 23 22 [1] [0] br 12 14 [2] [1] [0] res ? d *usestop usebt aor ? 0 ? usest send blocks: usepwd key: ????????????????????????????????????? aor anwer-on-request bt use block terminator st use sequence terminator pwd use password stop obey stop header (active low!) br bit rate ms1 modulator stage 1 ms2 modulator stage 2 pskcf psk clock frequency maxblk see maxblock feature reserved do not use * bit 15 and 24 must always be at ? 0 ? , otherwise malfunction will appear. lock bit (never transmitted) 1 pskcf 21 26 19 13 0000 0011 0101 to 2 0111 to 3 1001 to 4 1011 to 5 1101 to 6 1111 to 7 0 0 rf/2 0 1 rf/4 1 0 rf/8 1 1 reserved 0 0 0 direct 0 0 1 psk1 (phase change when input changes) 0 1 0 psk2 (phase change on bitclk if input high) 0 1 1 psk3 (phase change on rising edge of input) ??????????????????????????????????? o/p freq. data=1 data=0 1 0 0 fsk1 rf/8 rf/5 1 0 1 fsk2 rf/8 rf/10 1 1 0 fsk1a rf/5 rf/8 1 1 1 fsk2a rf/10 rf/8 0 0 direct 0 1 manchester 1 0 biphase 1 1 reserved 0 0 0 rf/8 bitrate_8cpb 0 0 1 rf/16 bitrate_16cpb 0 1 0 rf/32 bitrate_32cpb 0 1 1 rf/40 bitrate_40cpb 1 0 0 rf/50 bitrate_50cpb 1 0 1 rf/64 bitrate_64cpb 1 1 0 rf/100 bitrate_100cpb 1 1 1 rf/128 bitrate_128cpb ? 0 ? * * figure 7. memory map of block 0
e5551 rev. a2, 19-apr-00 6 (21) operating the e5551 general the basic functions of the e5551 are: supply ic from the coil, read data from the eeprom to the reader, write data into the ic and program these data into the eeprom. several errors can be detected to protect the memory from being written with the wrong data (see figure 21). supply the e5551 is supplied via a tuned lc circuit which is con- nected to the coil 1 and coil 2 pads. the incoming rf (actually a magnetic field) induces a current into the coil. the on-chip rectifier generates the dc supply voltage (v dd , v ss pads). overvoltage protection prevents the ic from damage due to high-field strengths. depending on the coil, the open-circuit voltage across the lc circuit can reach more than 100 v. the first occurrence of rf trig- gers a power-on reset pulse, ensuring a defined start-up state. read reading is the default mode after power-on reset. it is done by switching a load between the coil pads on and off. this changes the current through the ic coil, which can be detected from the reader unit. start-up the many different modes of the e5551 are activated after the first readout of block 0. the modulation is off while block 0 is read. after this set-up time of 256 field clock periods, modulation with the selected mode starts. any field gap during this initialization will restart the complete sequence. read datastream the first block transmitted is block 1. when the last block is reached, reading restarts with block 1. block 0, which contains mode data, is normally never transmitted. how- ever, the mode register is continuously refreshed with the contents of eeprom block 0. iac 125 khz energy data tuned lc reader coil e5551 figure 8. application circuit v damping on damping off read data with configured modulation and bitrate coil 1 ? coil 2 * fc ? > field clocks loading block 0 (256 fc 2 ms) 2 ms power-on reset figure 9. voltage at coil1/coil2 after power-on
e5551 rev. a2, 19-apr-00 7 (21) block sequence bit period last bit first bit last bit first bit ????? ????? data bit ? 1 ? ????? ????? data bit ? 1 ? data bit ? 1 ? waveforms for different modulations manchester fsk psk terminator not suitable for biphase modulation first bit ? 0 ? or ? 1 ? block terminator sequence terminator v coil 1 ? coil 2 figure 10. terminators ????? block 1 ???? block 2 ????? block 7 ????? block 1 ???? block 2 ? ? ? ????? ????? block 1 ???? ???? block 2 ????? ????? block 7 ???? ???? block 1 ???? ???? block 2 ? ? ?? ?? ????? ????? block 1 ????? ????? block 2 ????? ????? block 7 ????? ????? block 1 ????? ????? block 2 ? ? ? ? ? ? ? ? ? ? ? ? ???? ???? block 1 ???? ???? block 2 ????? ????? block 7 ???? ???? block 1 ????? ????? block 2 ? ? ?? ?? ?? ?? ? ? ?? ?? ? ? ?? ?? 0 0 0 0 loading block 0 loading block 0 loading block 0 loading block 0 block terminator sequence terminator ??? off st bt ??? off ??? ??? on ??? ??? off ??? ??? off ??? ??? on ??? ??? on ??? ??? on figure 11. read data streams and terminators block 1 block 4 block 5 block 1 block 2 maxblk = 5 maxblk = 2 maxblk = 0 block 1 block 2 block 1 block 2 block 1 block 0 block 0 block 0 block 0 block 0 0 0 0 loading block 0 loading block 0 loading block 0 figure 12. maxblk examples
e5551 rev. a2, 19-apr-00 8 (21) maxblock feature if it is not necessary to read all user data blocks; the maxblk field in block 0 can be used to limit the number of blocks read. for example, if maxblk = 5, the e5551 repeatedly reads and transmits only blocks 1 to 5 (see figure 11). if maxblk is set to ? 0 ? , block 0 ? which is normally not transmitted ? can be read. terminators the terminators are (optionally selectable) special damping patterns, which may be used to synchronize the reader. there are two types available; a block terminator which precedes every block, and a sequence terminator which always follows the last block. the sequence terminator consists of two consecutive block terminators. the terminators may be individually enabled with the mode bits st (sequence terminator enable) or bt (block terminator enable). note: it is not possible to include a sequence terminator in a transmission where maxblk = 0. direct access the direct access command allows the reading of an indi- vidual block by sending the op-code ( ? 10 ? ), the lock-bit and the 3-bit address. note: pwd has to be 0. modulation and bitrate there are two modulator stages in the e5551 (see figure 4) whose mode can be selected using the appropriate bits in block 0 (ms1[1:0] and ms[2:0]). also the bitrate can be selected using br[2:0] in block 0. these options are described in detail in figures 21 through 26. anticollision mode when the aor bit is set, the ic does not start modulation after loading configuration block 0. it waits for a valid aor data stream (wake-up command) from the reader before modulation is enabled. the wake-up command consists of the op-code ( ? 10 ? ) folowing by a valid password. the ic will remain active until the rf field is turned off or a stop op-code is received. table 7. e5551 ? modes of operation pwd aor stop behavior of tag after reset / por stop function 1 1 0 anticollision mode: modulation starts after wake-up with a matching pwd programming needs valid pwd aor allows programing with read protection (no read after write) stop op-code ( ? 11 ? ) defeats modu- lation until rf field is turned off 1 0 0 password mode: modulation starts after reset programming needs valid pwd 0 1 0 modulation starts after wake-up command programming with modulation defeat without previous wake-up possible aor allows programing with read protection (no read after write) 0 0 0 modulation starts after reset direct access command programming without password x 0 1 see corresponding modes above stop op-code ignored, modulation continues until rf field is turned off
e5551 rev. a2, 19-apr-00 9 (21) v por loading block 0 no modulation (stop = 0, aor = 1) modulation on coil 1 ? coil 2 op-code ( ? 10 ? ) followed by valid password figure 13. answer-on-request (aor) mode enter aor mode power on reset read configuration wait for opcode + pwd (== wake up command) write damping pwd correct ? send block 1...maxblk until stop command internal reset sequence no yes tag init tags with aor = ? 1 ? , pwd = ? 1 ? , stop = ? 0 ? send stop command ? select single tag ? send opcode + pwd (== wake up command) decode data all tags read ? exit wait for t w > 2.5ms no yes base station field off ? > on figure 14. anticollision procedure
e5551 rev. a2, 19-apr-00 10 (21) rf_field gap write data field clock 1 0 start 1 10 damping write mode data clock load on load off >64 fcs = stop write programming read mode read mode writing modulation during read mode figure 15. signals during writing write data decoder 1 16324864 fail 0 fail 1 writing done figure 16. write data decoding schemes op 2 addr 0 op 11 password mode aor (wake-up command) standard write stop command op l l op 10 10 10 1 data bits 32 1 password 32 1 password 32 op l 10 direct access 2 addr 0 2 addr 0 1 data bits 32 figure 17. e5551 ? op-code formats write writing data into the ic occurs via the temic write method. it is based on interrupting the rf field with short gaps. the time between two gaps encodes the ? 0/1 ? information to be transmitted. start gap the first gap is the start gap which triggers write mode. in write mode, the damping is permanently enabled which eases gap detection. the start gap may need to be longer than subsequent gaps in order to be detected reliably. a start gap will be detected at any time after block 0 has been read (field-on plus approximately 2 ms).
e5551 rev. a2, 19-apr-00 11 (21) start of writing rf read mode write mode (start gap) figure 18. start of writing decoder the duration of the gaps is usually 50 to 150 s. the time between two gaps is nominally 24 field clocks for a ? 0 ? and 56 field clocks for a ? 1 ? . when there is no gap for more than 64 field clocks after previous gap, the idic exits write mode; it starts with programming if the correct number of valid bits were received. if there is a gap fail ? i.e., one or more of the intervals did represent not a valid ? 0 ? or ? 1 ? ? the ic does not program, but enters read mode beginning with block 1, bit 1. writing data into the e5551 the e5551 expects a two bit op-code first. there are two valid op-codes ( ? 10 ? and ? 11 ? ). if the op-code is invalid, the e5551 starts read mode beginning with block 1 after the last gap. the op-code ( ? 10 ? ) is followed by different information (see figure 16): standard writing needs the op-code, the lock bit, the 32 data bits and the 3-bit block address. writing with usepwd set requires a valid password between op-code and address/data bits. in aor mode with usepwd, op-code and a valid password are necessary to enable modulation. the stop op-code is used to silence the e5551 (dis- able damping until power is cycled). note : the data bits are read in the same order as written. stop op-code the stop op-code ( ? 11 ? ) is used to stop modulation until a power-on reset occurs. this feature can be used to have a steady rf field where single transponders are collected one by one. each ic is read and than disabled, so that it does not interfere with the next ic. note: the stop op-code should contain only the two op-code bits to disable the ic. any additional data sent will not be ignored, and the ic will not stop modulation. standard op-code stop op-code 0 1 read mode write mode start gap more data ... > 64 clocks 1 1 figure 19. op-code transmission password when password mode is on (usepwd = 1), the first 32 bits after the op-code are regarded as the password. they are compared bit-by-bit with the contents of block 7, starting at bit 1. if the comparison fails, the ic will not program the memory, but restart in read mode at block 1 once writing has completed. notes: if pwd is not set, but the ic receives a write datastream containing any 32 bits in place of a pass- word, the ic will enter programming mode. in password mode, maxblk should be set to a value below 7 to prevent the password from being trans- mitted by the e5551. every transmission of 2 op-code bits, 32 password bits, one lock bit, 32 data bits and 3 address bits (= 70 bits) needs about 35 ms. testing all 2 32 possible combinations (about 4.3 billion) takes about 40,000 h, or over four years. this is a sufficient password protection for a general-purpose idic.
e5551 rev. a2, 19-apr-00 12 (21) 16 ms no modulation write mode check v hv on modulation operation write vpp/lock ok? program eeprom read 0.12 ms writing done (> 64 clocks since last gap) programming ends reading starts programming starts hv on for testing if vpp is ok (hv at eeproms) pp figure 20. programming v 16 ms read programming block read next block programming with updated modes write data into the ic (e.g., new bitrate) (= block 0) coil 1 ? coil 2 figure 21. coil voltage after programming of block 0 programming when all necessary information has been written to the e5551, programming may proceed. there is a 32-clock delay between the end of writing and the start of pro- gramming. during this time, vpp ? the eeprom programming voltage ? is measured and the lock bit for the block to be programmed is examined. further, vpp is continually monitored throughout the programming cycle. if at any time vpp is too low, the chip enters read mode immediately. the programming time is 16 ms. after programming is done, the e5551 enters read mode, starting with the block just programmed. if either block or sequence terminators are enabled, the block is pre- ceded by a block terminator. if the mode register (block 0) has been reprogrammed, the new mode will be activated after the just-programmed block has been transmitted using the previous mode. error handling several error conditions can be detected to ensure that only valid bits are programmed into the eeprom. there are two error types which lead to different actions. errors during writing there are four detectable errors which could occur during writing data into the e5551: wrong number of field clocks between two gaps the op-code is neither the standard op-code ( ? 10 ? ) nor the stop op-code ( ? 11 ? ) password mode is active but the password does not match the contents of block 7 the number of bits received is incorrect; valid bit counts are standard write 38 bits (pwd not set) password write 70 bits (pwd set) aor wake-up 34 bits stop command 2 bits if any of these four conditions are detected, the ic starts read mode immediately after leaving write mode. reading starts with block 1.
e5551 rev. a2, 19-apr-00 13 (21) errors during programming if writing was successful, the following errors could prevent programming: the lock bit of the addressed block is set v pp is too low in these cases, programming stops immediately. the ic reverts to read mode, starting with the currently addressed block. power-on reset loading block 0 read op-code password number of bits lock bit write mode ok ok ok ok hv program ok ok addr 1 addr current stop fail fail fail fail fail fail 11 10 figure 22. functional diagram of the e5551
e5551 rev. a2, 19-apr-00 14 (21) rf-field 9 2 1 16 8 18 18 9 16 16 1 8 916 9 2 1 16 8 18 916 inverted modulator data stream 1001 8 fc 8 fc data rate = 10 manchester coded 50 field clocks (fc) signal figure 23. example of manchester coding with data rate rf/16 rf-field 9 2 1 16 818 18 9 16 16 1 8 916 9 2 1 16 8 18916 inverted modulator signal biphase coded data stream 1001 8 fc 8 fc data rate = 10 50 field clocks (fc) figure 24. example of biphase coding with data rate rf/16
e5551 rev. a2, 19-apr-00 15 (21) data stream 1001 data rate= 10 rf-field 15 18 18 18 515 inverted modulator signal 40 field clocks (fc) f = rf/8, 0 f = rf/5 1 1 figure 25. example of fsk coding with data rate rf/40, sub- carrier f 0 = rf/8, f 1 = rf/5 data stream 001 10 rf-field 2 1 8 9 161 8 161 8 161 8 16 1 8 16 1 8 inverted modulator signal subcarrier rf/2 1 8 fc 8 fc data rate = 16 field clocks (fc) figure 26. example of psk1 coding with data rate rf/16
e5551 rev. a2, 19-apr-00 16 (21) datas stream 001 10 rf-field 2 1 8 9 161 8 161 8 161 8 16 1 8 16 1 8 inverted modulator signal subcarrier rf/2 1 8 fc 8 fc data rate = 16 field clocks (fc) figure 27. example of psk2 coding with data rate rf/16 data stream 1001 8 fc 8 fc data rate = 10 rf-field 2 1 8 9 161 8 161 8 161 8 16 1 8 16 1 8 inverted modulator signal sub carrier rf/2 16 field clocks (fc) figure 28. example of psk3 coding with data rate rf/16
e5551 rev. a2, 19-apr-00 17 (21) ~ coil 1 coil 2 v dd v ss = 2 v i dd v pp coil ? 1.5 v figure 29. measurement setup for i dd coil 1 mod coil 2 100 ~ 2 v ~ 2 v 100 figure 30. simplified damping circuit application example i 125 khz coil 1 (pin 8) coil 2 (pin 1) 2.2 nf to read amplifier 360 pf 4.2 mh from oscillator energy data f res 1 2 lc 125 khz ac 740 h input capacitance 5 pf static, 25 pf dynamic e5551 figure 31. typical application circuit
e5551 rev. a2, 19-apr-00 18 (21) absolute maximum ratings parameters symbol value unit maximum dc current into coil 1/ coil 2 i coil 10 ma maximum ac current into coil 1/ coil 2, f = 125 khz i coil pp 20 ma power dissipation (dice) 1) p tot 100 mw electro-static discharge maximum to mil-standard 883 c method 3015 v max 2000 v operating ambient temperature range t amb ? 40 to +85 c storage temperature range 2) t stg ? 40 to +125 c maximum assembly temperature for less than 5 min 3) t sld +150 c notes: 1) free-air condition, time of application: 1 s 2) data retention reduced 3) assembly temperature of 150 c for less than 5 minutes does not affect the data retention. stresses above those listed under ? absolute maximum ratings ? may cause permanent damage to the device. operating characteristics t amb = 25 c; f rf = 125 khz, reference terminal is v ss parameters comments symbol min. typ. max. unit rf frequency range f rf 100 125 150 khz supply current read and write over the full supply current (see figure 27) read and write over the full temperature range i dd 5 7.5 a (see figure 27) programming over the full temperature range i dd 100 200 a clamp voltage 10 ma current into coil1/2 v cl 9.5 11.5 v programming voltage from on-chip hv- generator v pp 16 20 v programming time t p 18 ms startup time t startup 4 ms data retention 1) t retention 10 years programming cycles 1) n cycle 100 000 supply voltage read and write v dd 1.6 v supply voltage read-mode, t = ? 30 c v dd 2.0 v coil voltage read and write v coil pp 6.0 v coil voltage programming, rf field not damped v coil pp 10 v damping resistor r d 300 note 1) since eeprom performance may be influenced by assembly and packaging, we can confirm the parameters for dow (= die-on-wafer) and ics assembled in standard package.
e5551 rev. a2, 19-apr-00 19 (21) chip dimensions ( m)
e5551 rev. a2, 19-apr-00 20 (21) package information technical drawings according to din specifications package so8 dimensions in mm 5.00 4.85 0.4 1.27 3.81 1.4 0.25 0.10 5.2 4.8 3.7 3.8 6.15 5.85 0.2 85 14
e5551 rev. a2, 19-apr-00 21 (21) ozone depleting substances policy statement it is the policy of temic semiconductor gmbh to 1. meet all present and future national and international statutory requirements. 2. regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. it is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (odss). the montreal protocol ( 1987) and its london amendments ( 1990) intend to severely restrict the use of odss and forbid their use within the next ten years. various national and international initiatives are pressing for an earlier ban on these substances. temic semiconductor gmbh has been able to use its policy of continuous improvements to eliminate the use of odss listed in the following documents. 1. annex a, b and list of transitional substances of the montreal protocol and the london amendments respectively 2. class i and ii ozone depleting substances in the clean air act amendments of 1990 by the environmental protection agency (epa) in the usa 3. council decision 88/540/eec and 91/690/eec annex a, b and c (transitional substances) respectively. temic semiconductor gmbh can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances. ddddd we reserve the right to make changes to improve technical design and may do so without further notice . parameters can vary in different applications. all operating parameters must be validated for each customer application by the customer. should the buyer use temic semiconductors products for any unintended or unauthorized application, the buyer shall indemnify temic semiconductors against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. data sheets can also be retrieved from the internet: http://www.temic?semi.com temic semiconductor gmbh, p.o.b. 3535, d-74025 heilbronn, germany telephone: 49 (0)7131 67 2594, fax number: 49 (0)7131 67 2423

▲Up To Search▲

Price & Availability of E5551A-DIT

	To Download E5551A-DIT Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .